Trim DAC Design with Minimum DNL for Self-Trim with Self-Test Schemes

High precision mixed-signal design strongly depends on trimming techniques to overcome manufacturing induced variability, of which the digital trimming is the most popular approach. The central element of a digitally driven trim circuit is the trim DAC. Whilst it needs to be simple and cheap its electrical performance in the digital to analogue conversion process will affect the trim result. In this paper we analyse the trimmed distribution as a function of the DNL performance of the trim DAC. Of particular concern is the shaping of the distribution by comparator based self-calibration schemes. A minimum DNL trim DAC design is proposed that overcomes unwanted distribution tails. Eliminating distribution tails is a design goal for any type of trimming but it is crucially important if an on-chip self-test scheme shall be added to the self-trimming. A simulation model for the trimmed distribution is compared to actual silicon results of standard and minimum-DNL trim DACs.