On Pre/Post-Bond Testing and Calibrating SAR ADC Array in 3-D CMOS Imager

This paper presents pre/post-bond testing and calibration techniques for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The underlying idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of its digital-to-analog converter (DAC) capacitor array (C-Array). During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. Then, during the post-bond stage, we utilize the digital resources from the image signal processor (ISP) die to perform more thorough characterization and calibration of the ADC array. Simulation results are presented to validate the proposed techniques.