Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes

Author

Fonseca, R. Alves ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Badereddine, N.

Author_Institution

CNRS, LIRMM Univ. de Montpellier II, Montpellier, France

fYear

2010

fDate

24-28 May 2010

Firstpage

132

Lastpage

137

Abstract

In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.

Keywords

SRAM chips; fault tolerant computing; system-on-chip; SRAM core-cells; memory size variation; power supply voltage variation; resistive value variation; resistive-bridging defect analysis; size 40 nm; size 65 mm; size 90 nm; static random access memory; technology nodes; temperature variation; Access protocols; Electricity supply industry; Hardware; Power supplies; Power system modeling; Random access memory; Temperature; Testing; Timing; Voltage; SRAM; core-cell; fault modeling; resistive-bridge;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2010 15th IEEE European

Conference_Location

Praha

ISSN

1530-1877

Print_ISBN

978-1-4244-5834-9

Electronic_ISBN

1530-1877

Type

conf

DOI

10.1109/ETSYM.2010.5512768

Filename

5512768