DocumentCode
3054151
Title
On optimizing BIST-architecture by using OBDD-based approaches and genetic algorithms
Author
Ökmen, Can ; Keirn, M. ; Krieger, Rolf ; Becker, Bernd
Author_Institution
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear
1997
fDate
27 Apr-1 May 1997
Firstpage
426
Lastpage
431
Abstract
We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-in-Self-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, the hardware-design of the actual BIST-structure is optimized. Experimental results are given to demonstrate the quality of our approach
Keywords
built-in self test; genetic algorithms; BIST architecture; OBDD; built in self test; genetic algorithm; hardware design; optimization; weighted random pattern testing; Built-in self-test; Circuit faults; Computer science; Constraint optimization; Fault detection; Genetic algorithms; Hardware; Optimization methods; Test pattern generators; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-7810-0
Type
conf
DOI
10.1109/VTEST.1997.600327
Filename
600327
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