• DocumentCode
    3054184
  • Title

    Optimization of a saddle-like FinFET by device simulation for sub-50nm DRAM application

  • Author

    Chang, H.-C. ; Kuo, P.-S. ; Peng, C.-Y. ; Chen, Y.-T. ; Chen, W.-Y. ; Liu, C.W.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper, we have numerically investigated the electrical characteristics of a saddle-like FinFET for sub-50nm DRAMs with a 3D device simulator.
  • Keywords
    DRAM chips; MOSFET; optimisation; 3D device simulator; device simulation; saddle-like FinFET; sub-50nm DRAM application; Capacitance; Circuit simulation; Delay effects; Doping profiles; Educational institutions; FinFETs; MOSFETs; Random access memory; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Device Research Symposium, 2009. ISDRS '09. International
  • Conference_Location
    College Park, MD
  • Print_ISBN
    978-1-4244-6030-4
  • Electronic_ISBN
    978-1-4244-6031-1
  • Type

    conf

  • DOI
    10.1109/ISDRS.2009.5378015
  • Filename
    5378015
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3054184