The impact of structural parameters on the electrical characteristics of GAA Silicon nanowire transistor

In this paper we investigate the electrical characteristics of silicon nanowire transistors using a fully ballistic quantum mechanical transport approach to analyze rectangular silicon nanowire transistor. We investigate the impact of structural parameters of nano scale Gate all around Silicon nano wire transistor (GAA-SNWT)on its electrical characteristics in subthreshold regime. In particular we show that increase in Source/Drain length (Ls ,LD) negligibly affects the current while increasing the Ls/LD will affect the gate capacitance. We also investigate the effect of increasing the gate underlap on short channel effects and on the switching speed of device. We show that if the L ¿¿¿ is increased the gate capacitance and DIBL will reduces while the Ion/Ioff ratio is increased. This parameter affect the power consumption and delay and is useful in nanowire design for low power application.