A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction

Author

Mauroux, P.-D. ; Virazel, A. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Pravossoudovitch, S. ; Godard, B. ; Festes, G. ; Vachez, L.

Author_Institution

LIRMM, Univ. of Montpellier, Montpellier, France

fYear

2010

fDate

24-28 May 2010

Firstpage

81

Lastpage

86

Abstract

Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered.

Keywords

SPICE; flash memories; ATMEL TSTAC eflash memory technology; ATMEL silicon data; Fowler-Nordheim tunneling effect; defect-induced failures; faulty behavior prediction; floating gate technology; functional layer; programming layer; resistive defect injection; two layer SPICE model; Dynamic programming; Flash memory; Functional programming; Logic programming; Nonvolatile memory; Predictive models; SPICE; Silicon; Testing; Voltage; Fowler-Nordheim; coupling effects; defects; electrical model; embedded Flash; fault modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2010 15th IEEE European

Conference_Location

Praha

ISSN

1530-1877

Print_ISBN

978-1-4244-5834-9

Electronic_ISBN

1530-1877

Type

conf

DOI

10.1109/ETSYM.2010.5512776

Filename

5512776