Title :
A design of 1T memory cells using channel traps for long data retention time
Author :
Chen, Y.-T. ; Huang, C.-F. ; Sun, H.-C. ; Wu, T.-Y. ; Ku, C.-Y. ; Liu, C.W. ; Hsu, Y.-C. ; Chen, J.-S.
Author_Institution :
Dept. of Electr. Eng., Taiwan Univ., Taiwan
Abstract :
This paper proposes a design of IT memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.
Keywords :
integrated circuit design; integrated memory circuits; low-power electronics; 1T memory cells; 3D integration compatibility; capacitorless structure; channel traps; drain current; long data retention time; low power consumption; Annealing; Data engineering; Degradation; Educational institutions; Electron traps; Energy consumption; Gold; Grain boundaries; Leakage current; Random access memory;
Conference_Titel :
Semiconductor Device Research Symposium, 2009. ISDRS '09. International
Conference_Location :
College Park, MD
Print_ISBN :
978-1-4244-6030-4
Electronic_ISBN :
978-1-4244-6031-1
DOI :
10.1109/ISDRS.2009.5378020
