Design of a Design-for-Digital-Testability Third-Order S-? Modulator

This paper presents the design of a third-order Σ-Δ modulator with the design-for-digital-testability (DfDT) structure for audio applications. The DfDT structure not only makes the Σ-Δ modulator digitally testable but also provides many test benefits such as a low hardware overhead, high fault observability, high test accuracy, and the capability of conducting at-speed tests. The zero in the noise transfer function of the proposed third-order Σ-Δ modulator vanishes the shaped quantization noises near the passband. As a result, the shaped noise correction of the digital tests is less significant. It helps improve the test accuracy of the digital tests. The simulation results with the fully-settled linear behavior plus noise (FSLB+N) model show that the peak SNDR and the dynamic range of the proposed third-order Σ-Δ modulator using conventional analog stimuli are 86.8 dB and 90.6 dB respectively at an over-sampling ratio (OSR) of 64. The SNDR differences between analog tests and those of the corresponding digital tests are in-between 0.9 dB and -1.4 dB with an average of 0.06 dB when the Σ-Δ modulator is not overloaded. In addition, both kinds of tests have similar effective resolution bandwidth results (ERBW). The simulation results confirm that the proposed Σ-Δ modulator can have a low test cost and thus is suitable for SoC and built-in self-test (BIST) integrations thanks to the DfDT structure.