DocumentCode
3054486
Title
Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond
Author
Wang, Xinlin ; Shahidi, Ghavam ; Oldiges, Phil ; Khare, Mukesh
Author_Institution
Res. Div., IBM Semicond. R&D Center, Hopewell Junction, NY
fYear
2008
fDate
9-11 Sept. 2008
Firstpage
309
Lastpage
312
Abstract
In this work, two different methodologies are used to quantitatively evaluate devices with metal high-k gate dielectrics for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band edge work function for the metal gate offers potential benefits for device scaling over conventional polysilicon gates for high performance (HP) application at the 32 nm CMOS technology node and beyond.
Keywords
CMOS integrated circuits; MOSFET; high-k dielectric thin films; oscillators; silicon; CMOS technology; MOSFET; aggressive channel length scaling; band edge work function; device characteristics; device scaling; high performance application; metal high-k gate dielectrics; polysilicon gates; ring oscillator delay calculations; size 32 nm; transistor performance gain; CMOS technology; Delay; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Performance gain; Research and development; Ring oscillators; Tunneling; channel length scaling; device scaling; high performance CMOS; metal high-k gate;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on
Conference_Location
Hakone
Print_ISBN
978-1-4244-1753-7
Type
conf
DOI
10.1109/SISPAD.2008.4648299
Filename
4648299
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