Jitter attenuation in T1 networks

The CS61574, a CMOS T1 line driver, clock recovery, and jitter-attenuator circuit is described. The jitter attenuator is an innovative mixed analog/digital circuit that consists of a 32-b FIFO and a capacitance-controlled crystal oscillator. The capacitance loading on the external crystal is digitally controlled by the CMOS circuitry to insure that the oscillator frequency matches the average incoming frequency of the recovered line signal. The FIFO buffers the incoming data, allowing the attenuator to provide up to 60 dB of attenuation of phase jitter. Unique attributes of this attenuator are the level of attenuation achieved, the absence of jitter aliasing, the absence of jitter peaking, and excellent jitter tolerance