Title :
A single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory architecture
Author :
Yamada, M. ; Tomonaga, E. ; Lin, M. ; Hung, J.
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.
Keywords :
audio signal processing; decoding; digital signal processing chips; digital television; large scale integration; memory architecture; reduced instruction set computing; television receivers; video signal processing; MPEG audio/video decoder; MPU; RISC processors; advanced unified memory architecture; flexible 2D graphic processor; optimal memory access operation; optimized memory architecture; single chip digital TV LSI; special arbitration algorithm; transport decoder; Costs; Decoding; Digital TV; Displays; Graphics; Hardware; Large scale integration; Memory architecture; Reduced instruction set computing; Video signal processing;
Conference_Titel :
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-5123-1
DOI :
10.1109/ICCE.1999.785216
