Title :
A surface potential based poly-Si TFT model for circuit simulation
Author :
Miyano, Soichiro ; Shimizu, Yoshiteru ; Murakami, Takahiro ; Miura-Mattausch, Mitiko
Author_Institution :
Res. Dept. 2, Adv. LCD Technol. Dev. Center Co. Ltd., Yokohama
Abstract :
We have developed a compact model of poly-Si TFTs based on complete surface-potential descriptions, including carrier trapping. The model was shown to be reliable for predicting high-speed circuit performances.
Keywords :
electron traps; hole traps; semiconductor device models; silicon; surface potential; thin film transistors; carrier trapping; circuit simulation; polysilicon thin film transistor; surface potential; Charge carrier processes; Circuit simulation; Displays; Electron traps; Grain boundaries; Insulation; Poisson equations; Substrates; Thin film transistors; Voltage; Compact Model; Thin Film Transistor; Trap Modeling;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on
Conference_Location :
Hakone
Print_ISBN :
978-1-4244-1753-7
DOI :
10.1109/SISPAD.2008.4648315
