A General Approach to Power Trace Alignment for the Assessment of Side-Channel Resistance of Hardened Cryptosystems

Cryptosystems are enabled to produce misaligned power traces in time domain either by inserting randomly dummy wait states or by exploiting a random clock generator, which can be seen as countermeasures to Differential Power Analysis (DPA), a well-known approach to mount side-channel attacks. In this paper, we consider such a random clock armed FPGA-based AES-128 cryptosytsem and try to remove this countermeasure by aligning the power traces in time domain. When increasing the clock frequency of the cryptosystem, the round peaks not only shift in time, but also change values in the amplitude domain. Therefore, a trace preprocessing capable to cope with this effect is needed before mounting the DPA attack. We propose a new general method to process misaligned traces by locating the amplitude domain shifted peak dynamically and at the same time by aligning the traces partially in time domain. The presented experimental results show that the proposed method works well and contributes to considerably improve the DPA attack on randomly misaligned traces in a large clock frequency range.