2PCDAL: Two-phase clocking dual-rail adiabatic logic

This paper presents a new dual-rail adiabatic logic which called 2PCDAL. Our proposed circuit is based on 2N2N2P structure. Unlike 2N2N2P which is driven by four-phase clocking, the proposed logic only needs two-phase clocking to operate. Compared with the proposed 2PCDAL and the other dual-rail quasi-adiabatic logic families of cell design, namely, 2N2N2P, CAL, ECRL, PAL, and PFAL, we show that the energy consumption of the proposed 2PCDAL inverter is almost the same as those of the other dual-rail adiabatic logics (i.e. 2N2N2P, ECRL, and PFAL) in the range of from 10 kHz to 10 MHz.