Real Time Cycle Slip Detection and Correction for APSK Modulation

An innovative algorithm is introduced for cycle slip detection and correction in communication systems that employ APSK modulation. The algorithm is well suited for carrier phase synchronizers that are based on phase locked loops, and it achieves significant improvement in BER performance without compromising spectral efficiency. A systematic approach for the selection of all main algorithm parameters is detailed. In particular, the 16-APSK scheme, (recommended in the DVB-S2 standard) is analyzed by assuming an AWGN channel, and simulation results in the presence of various channel impairments are presented. The results establish the superiority of the proposed algorithm over other known cycle slip handling techniques for PLL synchronization. Integration with state-of-the-art iterative synchronization is also considered.