Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling. By virtues of reduced intra-junction and punch-through leakage currents, threshold voltage controllability, and higher current drivability, SOI FinFETs are utilized in most recent CMOS circuits. In this work, half-pitch (HP) 32 nm SOI FinFETs are designed for LSTP considering GIDL by device simulation with regard to junction doping profile. For more accurate results, various models for carrier mobility, gate current, recombination, band-to-band and trap-assisted tunneling, and quantum effects have been activated.