Design of a multistage switching network for ATM

The authors propose a switching network that approaches a maximum throughput of 100% as buffering is increased. This self-routing switching network consists of simple 2×2 switching elements, distributors, and buffers located between stages and in the output ports. The switching network requires a speedup factor of two. The switch has log₂ N stages that move packets in store-and-forward fashion, thus incurring a latency of log₂ N time periods. The performance analysis of the switch under a uniform traffic pattern shows that the additional delay is small and a maximum throughput of 100% is achieved as buffering is increased