Title :
A multi-rate SerDes transceiver for IEEE 1394b applications
Author :
Longfei Wei ; Jinyue Ji ; HaiQi Liu ; Qiang Li
Author_Institution :
Centre for Commun. Circuits & Syst., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper presents an implementation of multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used at transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100Mb/s, 400Mb/s and 800Mb/s, supporting three different operating modes of S100b, S400b and S800b for IEEE 1394b. The chip has been fabricated using 0.13μm technology. The die area of transceiver is 2.9*1.6 mm2 including bonding pads and the total power dissipation is 284 mW with 1.2V and 3.3V supply voltages.
Keywords :
CMOS digital integrated circuits; equalisers; high-speed techniques; integrated circuit bonding; phase locked loops; power supplies to apparatus; synchronisation; transceivers; IEEE 1394b applications; S100b; S400b; S800b; bit rate 100 Mbit/s; bit rate 400 Mbit/s; bit rate 800 Mbit/s; bonding pads; chip fabrication; data rates; data recovery circuit; equalizer circuits; multirate SerDes transceiver; on-chip fully integrated phase locked loop; optimized linearity; phase interpolator-based clock; power 284 mW; power dissipation; receiver; serializer-deserializer transceiver; size 0.13 mum; transceiver die area; voltage 1.2 V; voltage 3.3 V; Clocks; Equalizers; Linearity; Phase locked loops; Receivers; Transceivers; Transmitters; 1394; SerDes; equalizer; firewire; pre-emphasis;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6419035
