Fabrication approach for lateral InGaAs tunnel transistors

Author

Wheeler, D. ; Kabeer, S. ; Yeqing Lu ; Vasen, T. ; Qin Zhang ; Guangle Zhou ; Clark, K. ; Haijun Zhu ; Yung-Chung Kao ; Fay, P. ; Kosel, T. ; Huili Xing ; Seabaugh, A.

Author_Institution

Dept. of Electr. Eng., Univ. of Notre Dame, Notre Dame, IN, USA

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

1

Lastpage

2

Abstract

In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO₂/Al₂O₃ high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.

Keywords

Zener effect; aluminium compounds; atomic layer deposition; dielectric materials; field effect transistors; gallium arsenide; hafnium compounds; indium compounds; semiconductor device manufacture; tunnel transistors; tunnelling; HfO₂-Al₂O₃; InGaAs; Zener tunneling current; atomic-layer deposition; gate dielectric; reverse bias; size 4 nm; transistor channel; tunnel FET; tunnel transistors; Aluminum oxide; FETs; Fabrication; Hafnium oxide; Indium gallium arsenide; Indium phosphide; Molecular beam epitaxial growth; Plasma temperature; Substrates; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-6030-4

Type

conf

DOI

10.1109/ISDRS.2009.5378160

Filename

5378160