• DocumentCode
    3057276
  • Title

    Built-in chaining: introducing complex components into architectural synthesis

  • Author

    Marwedel, Peter ; Landwehr, Birger ; Dömer, Rainer

  • Author_Institution
    Dept. of Comput. Sci., Dortmund Univ., Germany
  • fYear
    1997
  • fDate
    28-31 Jan 1997
  • Firstpage
    599
  • Lastpage
    605
  • Abstract
    Extends the set of library components which are usually considered in architectural synthesis by components with built-in chaining (BIC). For such components, the result of some internally computed arithmetic function is made available as an argument to some other function through a local connection. These components can be used to implement chaining in a data-path in a single component. Components with BIC are combinatorial circuits. They correspond to “complex gates” in logic synthesis. If compared to implementations with several components, components with BIC usually provide a denser layout, reduced power consumption and a shorter delay time. Multiplier/accumulators are the most prominent example of such components. Such components require new approaches for library mapping in architectural synthesis. In this paper, we describe an integer programming (IP) based approach taken in our OSCAR (Optimum Simultaneous sCheduling, Allocation and Resource assignment) synthesis system
  • Keywords
    circuit layout CAD; circuit optimisation; combinational circuits; high level synthesis; integer programming; power consumption; software libraries; OSCAR synthesis system; architectural synthesis; built-in chaining; combinatorial circuits; complex gates; complex library components; data-path; delay time; dense layout; high-level synthesis; integer programming; internally computed arithmetic function; library mapping; local connection; logic synthesis; multiplier/accumulators; reduced power consumption; register transfer level architecture; Arithmetic; CMOS technology; Circuit synthesis; Computer science; Delay effects; Energy consumption; High level synthesis; Libraries; Logic gates; Propagation delay;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    0-7803-3662-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1997.600342
  • Filename
    600342