Optimal design method for chip-area-efficient CMOS low-dropout regulator

Author

Ikeda, Shoji ; Ito, H. ; Ishihara, Noboru ; Masu, Kazuya

Author_Institution

Solutions Res. Lab., Tokyo Inst. of Technol., Yokohama, Japan

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

332

Lastpage

335

Abstract

This paper proposes a design method to minimize area of a CMOS low-dropout regulator (LDO) numerically. The new estimation technique for the value of the output voltage ripple under rapid load-current changes is derived, and thus the design procedure to minimize the chip area of the LDO is clarified. To verify the proposed method, the small-area LDO was designed by applying the proposed technique and fabricated in 65nm CMOS process. Measurement result shows the value of the output voltage ripple was suppressed less than 50mV when load current changes from 0 to 30mA in 1 μs at 1.2V output voltage with 1.8V power supply. And the LDO could be implemented with small chip area of 100μm × 100μm. The quiescent power consumption was 472μW.

Keywords

CMOS integrated circuits; low-power electronics; power consumption; power supply circuits; CMOS process; chip-area-efficient CMOS low-dropout regulator; current 30 mA; design procedure; estimation technique; load current; optimal design method; output voltage ripple; power 472 muW; power supply; quiescent power consumption; rapid load-current changes; size 65 nm; small-area LDO; voltage 1.8 V; CMOS integrated circuits; Capacitors; Equations; Logic gates; Mathematical model; Regulators; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6419039

Filename

6419039