Design and yields of 1200-V recessed-implanted-gate SiC vertical-channel JFETs for power switching applications

Author

Veliadis, V. ; Ha, H.C. ; Hearne, H. ; Howell, R. ; Van Campen, S. ; Urciuoli, D. ; Lelis, A. ; Scozzie, C.

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

1

Lastpage

2

Abstract

The paper presents the feasibility of a 1200-V normally-OFF VJFET based on the manufacturable single-implant no-epitaxial-regrowth design. For efficient power switching (low gate current, low on-state resistance, low switching losses, and high current-gain), the VJFET gate must be biased below its built-in potential value (unipolar mode operation). In unipolar mode, 1200-V recessed-implanted-gate (RIG) normally-OFF VJFETs exhibited prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirmed experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific ON-state resistance observed under high current-gain VJFET operation. Simulations were performed to fully explore the single-implant no-epitaxial-regrowth RIG VJFET design space.

Keywords

crystal growth; junction gate field effect transistors; power semiconductor switches; semiconductor device manufacture; silicon compounds; wide band gap semiconductors; SiC; power switching application; recessed implanted gate vertical channel JFET; single-implant no-epitaxial-regrowth design; unipolar mode operation; voltage 1200 V; Circuits; Doping; Educational institutions; Electrons; JFETs; Laboratories; Power system reliability; Silicon carbide; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-6030-4

Electronic_ISBN

978-1-4244-6031-1

Type

conf

DOI

10.1109/ISDRS.2009.5378163

Filename

5378163