An OMNeT++ based Network-on-Chip simulator for embedded systems

Network-on-Chip (NoC) was presented as a new System-on-Chip (SoC) paradigm to solve the problem associated with shared buses in multi-core systems by replacing the traditional bus based on-chip interconnections with packet-switched network architecture. The performance of NoCs depends on many influencing factors as e.g., network size, network topology, routing scheme, congestion avoidance method. Investigating the effects of different parameters and configurations on a simulation tool is preferred over a real hardware due to time and cost considerations. In this paper, an NoC simulator using OMNeT++ is built for investigating sparse matrix-vector multiplication (SMVM) using an NoC. More precisely, as an example for these investigations, two methods for increasing the NoC throughput are presented which are dynamic and asynchronous routings.