Title :
An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding
Author :
Yichao Lu ; Nanfan Qiu ; Zhixiang Chen ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability-based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB- and ISRB-MLGD with limited complexity increase.
Keywords :
computational complexity; iterative methods; parity check codes; reliability; computational complexity; error correct ability; finite field operations; integer operations; iterative double-reliability-based MLGD algorithm; majority-logic based message-passing; majority-logic decoding; nonbinary LDPC codes; nonbinary LDPC decoding; q-ary sum-product algorithm;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6419076