DocumentCode
3058325
Title
Solving constrained via minimization by compact linear programming
Author
Shi, C. J Richard
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1997
fDate
28-31 Jan 1997
Firstpage
635
Lastpage
640
Abstract
Via minimization is an important problem in integrated circuit layout and printed circuit board design. A linear (non-integral) programming approach to two-layer constrained via minimization (CVM) is presented. The approach finds optimum solutions for routings containing no more than three way splits, and guarantees provably good results for the general case. Most importantly, the size of linear programming formulation is polynomial in terms of the size of the CVM problem. The significance of the work lies in three aspects. First, since linear programming can be solved in polynomial time, the work thus provides, for the first time, a mathematical programming solution with computational efficiency comparable to known combinatorial CVM algorithms. Second, the compact linear programming approach is provably good and natural for general CVM, while previous restricted CVM algorithms are difficult to he extended to the general case. Third, the approach can handle additional constraints in a unified manner, and thus provides an efficient method for performance-driven layer assignment. The approach is based on some new graph-theoretic and polyhedron-combinatorial results presented on the structure of the CVM problem
Keywords
circuit layout CAD; circuit optimisation; graph theory; integrated circuit interconnections; integrated circuit layout; linear programming; minimisation; network routing; printed circuit layout; compact linear programming; computational efficiency; graph-theoretic results; integrated circuit layout design; mathematical programming solution; optimum routing solutions; performance-driven layer assignment; polyhedron-combinatorial results; printed circuit board design; two-layer constrained via minimization solution; Cities and towns; Computational efficiency; Integrated circuit layout; Linear programming; Minimization; Polynomials; Printed circuits; Routing; Transmission line theory; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
0-7803-3662-3
Type
conf
DOI
10.1109/ASPDAC.1997.600347
Filename
600347
Link To Document