The ITRS metrology roadmap

Author

Diebold, Alain C.

Author_Institution

Coll. of Nanoscale Sci. & Eng., U. Albany, Albany, NY, USA

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

1

Lastpage

2

Abstract

This paper was focused on the 2009 international technology metrology roadmap for semiconductors based on front end processes, interconnect, lithography, and process integration roadmaps. Recent measurement innovations for high-k-metal gate material stack and measurement necessary for new transistor design were discussed. Graphene was emphasized for characterisation and device applications and properties were analyzed using methods such as TEM, LEEM, nano-Raman and several scanned probe methods, and other multiscale simulations.

Keywords

CMOS integrated circuits; Raman spectra; dielectric materials; graphene; interconnections; lithography; low energy electron diffraction; semiconductor device measurement; semiconductor technology; transistors; transmission electron microscopy; C; ITRS metrology roadmap; LEEM; TEM; device applications; front end processes; graphene; high-k-metal gate material stack; interconnect; international technology metrology roadmap; lithography; multiscale simulations; nano-Raman spectroscopy; process integration; scanned probe methods; transistor design; CMOS process; Dielectric materials; Dielectric measurements; Educational institutions; Etching; Integrated circuit interconnections; Lithography; Metrology; Research and development; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-6030-4

Electronic_ISBN

978-1-4244-6031-1

Type

conf

DOI

10.1109/ISDRS.2009.5378220

Filename

5378220