Fault tolerant interconnect for on-wafer processor communication

A fault-tolerance scheme for efficiently reconfiguring the two-dimensional processor arrays implemented on a wafer is presented. This scheme can achieve near optimal yield for the target array, using minimal redundant circuits (processors and interconnection buses). It also displays short maximum restructured edge length. The scheme achieves high efficiency by maximally sharing the utilization of good processors between adjacent rows. The scheme is expected to be easily applicable to other topologies, and the cube-connected cycles network has shown to be efficiently reconfigured using it