Title :
Simulation study for suppressing corner effect in a saddle MOSFET for Sub-50 nm high density high performance DRAM cell transistor
Author :
Pervez, Syed Atif ; Kim, Heesang ; Park, Byung-Gook ; Shin, Hyungcheol
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
In this work, the reasons for the abnormal corner effect, its impact on the saddle MOSFET device characteristics, and possible approaches to suppress it are examined through simulation. Effectively suppressing the abnormal corner effects is important for application in sub-50 nm high density high performance DRAM cell transistor.
Keywords :
DRAM chips; MOS memory circuits; MOSFET; semiconductor device models; abnormal corner effect; high density high performance DRAM cell transistor; saddle MOSFET simulation; Controllability; Degradation; Doping; Educational institutions; Electrons; FinFETs; Leakage current; MOSFET circuits; Random access memory; Threshold voltage;
Conference_Titel :
Semiconductor Device Research Symposium, 2009. ISDRS '09. International
Conference_Location :
College Park, MD
Print_ISBN :
978-1-4244-6030-4
Electronic_ISBN :
978-1-4244-6031-1
DOI :
10.1109/ISDRS.2009.5378226
