Title :
Communication reliability improvement for WSI array processors
Author :
Jean, J.S.N. ; Kung, S.Y.
Author_Institution :
Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
Abstract :
A reconfiguration algorithm is proposed for two arrays, a one-and-half-track array and a two-and-half-track array. The algorithm considers a whole fault pattern all together and therefore makes no early blind decision. The reconfiguration algorithm can systematically enumerate all the placement possibilities and can handle the defects of switches/connections/wires by incorporating the restrictions into the contradiction graph. It is shown that much better array yield can be obtained for the two-and-half-track array. The one-and-half-track array, however, is still useful when run-time fault tolerance is considered
Keywords :
VLSI; fault tolerant computing; parallel processing; reliability; WSI array processors; communication reliability; contradiction graph; fault pattern; reconfiguration algorithm; run-time fault tolerance; Communication switching; Computer science; Hardware; Joining processes; Logic arrays; Parallel processing; Reliability engineering; Routing; Switches; Wires;
Conference_Titel :
Communications, 1990. ICC '90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on
Conference_Location :
Atlanta, GA
DOI :
10.1109/ICC.1990.117185