Self-timed 1-D ICT processor

Author

Pang, Johnson T C ; Choy, Oliver C S ; Chan, C.F. ; Cham, W.K.

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong

fYear

1997

fDate

28-31 Jan 1997

Firstpage

669

Lastpage

670

Abstract

This paper describes a LSI implementation of 1-D order-8 integer cosine transform (ICT) which can calculate either forward or reverse transformation. It is a standard-cell based design using 0.7 μm CMOS SLP DLM process. The chip´s performance is maximized with the fast computation algorithm and self-timed circuit technique. It consists of eight parallel self-timed pipelines. Each self-timed block is designed based on 2-phase handshaking protocol and variable delay concept. The die size is 5.7×4.1 mm with about 76 K transistors. This chip supports 16-bit I/O data and its data rate is up to 60 MHz

Keywords

CMOS digital integrated circuits; asynchronous circuits; digital signal processing chips; discrete cosine transforms; large scale integration; pipeline processing; timing; 0.7 μm CMOS SLP DLM process; 0.7 mum; 1D order-8 integer cosine transform; 2-phase handshaking protocol; 4.1 mm; 5.7 mm; 60 MHz; LSI implementation; fast computation algorithm; forward transformation; parallel self-timed pipelines; reverse transformation; self-timed 1-D ICT processor; self-timed circuit technique; variable delay concept; Circuits; Clocks; Delay estimation; Digital systems; Discrete cosine transforms; Discrete transforms; Kernel; Logic design; Protocols; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600356

Filename

600356