Life-stress relationship for thin film transistor gate line interconnects on flexible substrates

This work focuses on one particular failure mode and models its failure mechanism with respect to the appropriate agent of failure; specifically the stress-life relationship for gate line interconnects on flexible substrates. A dedicated test system and custom mask was specifically developed for this test set up to directly measure the gate line resistance for each cycle. Time to failure data was used to determine model parameters for an inverse power law as the accelerated life model as well as a Weibull life distribution. This model can then be used as a basis for modeling the source lines or even higher level modeling of the entire display.