Effect of input harmonic terminations on high efficiency class-B and class-F operation of PHEMT devices

Device level harmonic balance simulations are used to show that very high efficiency can be achieved in PHEMT class-B and class-F amplifiers if efforts are made to provide proper input as well as output harmonic terminations. The simulations use a gate capacitance model which accurately describes the C/sub gs/ versus V/sub gs/ dependence for the PHEMT and are illustrated with waveform and dynamic loadline plots which relate directly to the idealized textbook view of high efficiency operation.