Data level parallel processing for object recognition on Recursive Torus Architecture

Author

Matsuyama, T. ; Asada, N. ; Aoyama, M. ; Kamashita, A. ; Asazu, H. ; Yamamoto, H. ; Ogawa, K.

Author_Institution

Dept. of Inf. Technol., Okayama Univ., Japan

fYear

1995

fDate

18-20 Sep 1995

Firstpage

90

Lastpage

97

Abstract

The paper gives a brief overview of the hardware design of RTA/1 (with 1024 PEs), a parallel machine designed based on the Recursive Torus Architecture (T. Matsuyama et al., 1993). We developed a small scale prototype machine with 16 PEs, RTA/0, to evaluate its performance. Then, we propose a scheme of data level parallel processing on RTA/1 and demonstrate its utilities by implementing complex parallel processes for bottom up object recognition on RTA/0

Keywords

object recognition; parallel architectures; parallel machines; RTA/1; bottom up recognition; complex parallel processes; data level parallel processing; hardware design; object recognition; parallel machine; recursive torus architecture; small scale prototype machine; Concurrent computing; Data structures; Filtering algorithms; Hardware; Image edge detection; Object recognition; Parallel machines; Parallel processing; Prototypes; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

Conference_Location

Como

Print_ISBN

0-8186-7134-3

Type

conf

DOI

10.1109/CAMP.1995.521023

Filename

521023