Title :
An FPGA-based point pattern matching processor with application to fingerprint matching
Author :
Ratha, Nalini K. ; Jain, Anil K. ; Rover, Diane T.
Author_Institution :
Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Abstract :
We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to fingerprint matching using Splash 2-an attached processor for SUN SPARCstation hosts. Each of the field programmable gate array (FPGA)-based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is verified. The final control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a fingerprint. With 65 features per fingerprint, the matching speed has been projected at the rate of 2.6*105 fingerprints/sec. The synthesized coprocessor was tested on a 10000 fingerprint database
Keywords :
circuit analysis computing; coprocessors; field programmable gate arrays; fingerprint identification; hardware description languages; logic CAD; pattern matching; reconfigurable architectures; 17.1 MHz; SUN SPARCstation hosts; Splash 2; VHDL; behavioral modeling; coprocessor design; coprocessor synthesis; feature vector; field programmable gate array; fingerprint database; fingerprint matching; high-performance coprocessor; peak speed; point feature matching coprocessor; point pattern matching processor; program logic verification; reconfigurable hardware; simulation tools; synthesis tools; synthesized coprocessor; Application software; Bifurcation; Computer science; Coprocessors; Field programmable gate arrays; Fingerprint recognition; Hardware; Pattern matching; Spatial databases; Sun;
Conference_Titel :
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location :
Como
Print_ISBN :
0-8186-7134-3
DOI :
10.1109/CAMP.1995.521064
