DocumentCode
3062158
Title
High level synthesis of a defect detector
Author
Verdier, F.S. ; Zavidovique, B.
Author_Institution
Systeme de Perception Lab., DGA/ETCA/CREA, Arcueil, France
fYear
1995
fDate
18-20 Sep 1995
Firstpage
411
Lastpage
415
Abstract
We present an innovative methodology aimed at rapidly designing image processing systems. Within this environment the first step consists in emulating an IP algorithm on a massively parallel dedicated computer. A compact and functionally equivalent VLSI circuit is then derived by using a high level synthesis system called ALPHA. The whole methodology is presented and illustrated with an IP algorithm effectively designed
Keywords
VLSI; high level synthesis; image processing; image processing equipment; network synthesis; parallel processing; special purpose computers; virtual machines; ALPHA; VLSI circuit; defect detector; high level synthesis; image processing algorithm emulation; image processing system design; massively parallel dedicated computer; Control system synthesis; Data flow computing; Data mining; Detectors; Emulation; Flow graphs; Hardware; High level synthesis; Image processing; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location
Como
Print_ISBN
0-8186-7134-3
Type
conf
DOI
10.1109/CAMP.1995.521066
Filename
521066
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