Title :
Scenarios of CMOS scaling
Author :
Wang, Kang L. ; Lynch, William T.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
This paper attempts to provide plausible scenarios of scaled CMOS. We address the issues, challenges and opportunities for research and development in the quest of ultra dense CMOS. We examine several possible paradigms of clever devices and their integration. The long-term effort, beyond the post shrink era of CMOS, to be discussed include functional device clusters and alternative computational architectures for satisfying the information need in the next Century
Keywords :
CMOS integrated circuits; CMOS scaling; computational architectures; functional device clusters; paradigms; post shrink era; scaled CMOS; ultra dense CMOS; CMOS technology; Computer architecture; Costs; Moore´s Law; Power dissipation; Power generation economics; Random access memory; Research and development; Stacking; Throughput;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-4306-9
DOI :
10.1109/ICSICT.1998.785772
