Title :
Design of an ASIP processor for MD5 hash algorithm
Author :
Mehrabani, Y.S. ; Eshghi, Mohammad ; Mehrabani, Y.S.
Author_Institution :
Dept. of Comput. Eng., Islamic Azad Univ., Tehran, Iran
Abstract :
ASIP (Application Specific Instruction set Processor) makes compromise between ASIC (Application Specific Integrated Circuit) and DSP (Digital Signal Processing) processor in terms of speed, cost, and flexibility parameters. Considering these unique properties of ASIP processors, design of an ASIP-based processor for MD5 (Message-Digest 5) hash algorithm is presented in this paper for the first time. Three structures named RCO (Register Configuration 0), RC1, and RC2 have been proposed. The third design has the minimum number of clock pulses in order to execute specific instructions. Proposed design has been simulated with VHDL code in the behavioral level of abstraction.
Keywords :
application specific integrated circuits; cryptography; digital signal processing chips; hardware description languages; instruction sets; ASIC; ASIP processor design; ASIP processors; DSP; MD5 hash algorithm; RC1; RC2; RCO; VHDL code; application specific instruction set processor; application specific integrated circuit; clock pulses; digital signal processing processor; message-digest 5 hash algorithm; register configuration 0; Telecommunications; ASIP; MD5 hash algorithm; RTL; register configuration;
Conference_Titel :
Telecommunications Forum (TELFOR), 2012 20th
Conference_Location :
Belgrade
Print_ISBN :
978-1-4673-2983-5
DOI :
10.1109/TELFOR.2012.6419269
