Novel Ti-SALICIDE process with low resistivity for sub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n⁺poly-Si lines and n⁺ diffusion layers using pre-amorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2 μm CMOS device and beyond. Pre-amorphization enhances the phase transformation from C₄₉ Ti_xSi _x to C₅₄ TiSi₂ and lowers the transformation temperature by 80°C so that it occurs before conglomeration in narrow lines. The sheet resistance of TiSi₂ on heavily As doped poly-Si lines is 3.7 Ω/□ and 3.8 Ω/□ for the samples pre-amorphized by Ge and Sb implantations even with line width down to 0.2 μm. There is less leakage in a Ti-SALICIDE diode with pre-amorphization than without it. The probable reasons and mechanisms are discussed