An algorithmic analog-to-digital converter using unity-gain buffers

Author

Ogawa, Satomi ; Watanabe, Kenzo

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

fYear

1990

fDate

13-15 Feb 1990

Firstpage

227

Lastpage

231

Abstract

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8 b and a conversion rate up to 10 Mb/s are attainable with presently available 3-μm CMOS technologies. Videofrequency operation may also be possible with finer linewidths. The component requirement is minimal, and thus it is best suited for an analog interface in application-specific integrated circuits. A prototype converter built using discrete components has confirmed the principles of operation

Keywords

CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; buffer circuits; computer architecture; digital simulation; electronic engineering computing; pipeline processing; 3 micron; CMOS technologies; SPICE simulations; algorithmic analog-to-digital converter; analog interface; application-specific integrated circuits; bipolar circuit; cascade; cyclic architecture; error analysis; iterative method; pipeline A/D converter architectures; prototype; recursive algorithm; unity-gain buffers; Analog-digital conversion; Analytical models; Application specific integrated circuits; CMOS technology; Error analysis; Integrated circuit technology; Iterative algorithms; Pipelines; Prototypes; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 1990. IMTC-90. Conference Record., 7th IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/IMTC.1990.66004

Filename

66004