Implementation of a low power 128-point FFT

Author

Jia, Lihong ; Li, Bingxin ; Gao, Yonghong ; Tenhunen, Hannu

Author_Institution

Electron. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden

fYear

1998

fDate

1998

Firstpage

369

Lastpage

372

Abstract

In this paper a low power 128 point fast Fourier transform (FFT) processor is implemented based on our new VLSI-oriented FFT algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. A new management of the on-chip memory further reduce its power consumption. This FFT processor has been designed in 0.6 μm 3.3 V triple-metal CMOS process with an area of 10 mm². The chip is capable of computing a 128 point FFT every 3 μs and the power dissipation is 400 mW at 50 MHz input frequency

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; low-power electronics; parallel algorithms; parallel architectures; pipeline arithmetic; 0.6 micron; 3.3 V; 500 MHz; VLSI-oriented FFT algorithm; implementation; low power FFT processor; minimized number of complex multiplications; on-chip memory management; pipelined architecture; power dissipation; radix-2/4/8; triple-metal CMOS process; Algorithm design and analysis; CMOS process; Energy consumption; Energy management; Frequency; Memory management; Power dissipation; Random access memory; Read-write memory; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785898

Filename

785898