A scalable real-time image processing pipeline

Author

Jonker, Pieter P. ; Komen, Erwin R.

Author_Institution

Pattern Recognition Section, Delft Univ. of Technol., Netherlands

fYear

1992

fDate

30 Aug-3 Sep 1992

Firstpage

142

Lastpage

146

Abstract

To speed up image processing in the field of robot vision and industrial inspection, a pipeline element was made which is able to perform fast cellular logic operations. This Cellular Logic Processing Element (CLPE) is able to process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI-device which includes a Writable Logic Array for the storage of sets of 3×3 structuring elements which define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed grey value processing and cellular logic processing

Keywords

digital signal processing chips; image processing; image processing equipment; pipeline processing; real-time systems; CMOS VLSI-device; Cellular Logic Processing Element; Writable Logic Array; binary images; cellular logic operations; cellular logic processing; industrial inspection; mixed grey value processing; robot vision; scalable real-time image processing pipeline; Buildings; CMOS logic circuits; CMOS process; Image processing; Inspection; Logic arrays; Pipelines; Pixel; Robot vision systems; Service robots;

fLanguage

English

Publisher

ieee

Conference_Titel

Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on

Conference_Location

The Hague

Print_ISBN

0-8186-2925-8

Type

conf

DOI

10.1109/ICPR.1992.202151

Filename

202151