A performance model for ATM switches with internal speedup

Author

Iun, Dennis P C ; Cao, X.R.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong

Volume

2

fYear

1996

fDate

11-13 Dec 1996

Firstpage

1352

Abstract

In this paper we study a non-blocking ATM switch with internal speedup. Modifying the model in Cao (1995), we can obtain the maximum throughput of the switch; approximating the output process by a discrete-time Markov modulated process, we can calculate the cell loss probabilities at the output buffers. In our approach, the incoming traffic is considered to have correlated destinations and asymmetric routing probabilities. Simulation results illustrate that the approach is very accurate

Keywords

Markov processes; asynchronous transfer mode; packet switching; probability; queueing theory; switching networks; telecommunication network routing; asymmetric routing probabilities; cell loss probabilities; correlated destinations; discrete-time Markov modulated process; internal speedup; maximum throughput; nonblocking ATM switch; output process; performance model; Analytical models; Asynchronous transfer mode; Fabrics; Information technology; Load modeling; Probability; Routing; Switches; Throughput; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Decision and Control, 1996., Proceedings of the 35th IEEE Conference on

Conference_Location

Kobe

ISSN

0191-2216

Print_ISBN

0-7803-3590-2

Type

conf

DOI

10.1109/CDC.1996.572694

Filename

572694