Channel formation for 0.15 μm CMOS using through-the-gate implantation

Author

Montree, A.H. ; Ponomarev, Y.V. ; Baks, W.M. ; van Brandenburg, A.C.M.C. ; Dachs, C. ; Roes, R.F.M. ; Schmitz, J. ; Stolk, P.A. ; Tuinhout, H.P.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1999

fDate

1999

Firstpage

10

Lastpage

13

Abstract

Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained

Keywords

CMOS integrated circuits; MOSFET; integrated circuit technology; ion implantation; 0.15 micron; CMOS technology; NMOS device; Si:B; boron super-steep retrograde well; channel formation; front-end optimization; through-the-gate implantation; transistor matching; Boron; Capacitors; Design for quality; Energy measurement; Implants; MOS devices; Oxidation; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.785987

Filename

785987