The AES Design Space Exploration with a Soft IP Generator

Advanced encryption standard (AES) is a new standard for data encryption and decryption. There is a lot of relevant research so far. However, how to find out the suitable design according to the demand has been became an important issue. Hence, we consult different improvement methods from relevant research. To do the design space exploration of AES hardware circuit design with the modeling of parameterized soft IP generator. We choose non-feedback mode AES design, which can be offered higher security. In this paper, a soft IP generator that can create AES module is proposed. It can be applied to AES IP designs that fit in with different requirements by designer. It provides an interface that can help to easily manage the Verilog synthesizable RTL code module, and remove unnecessary functions in order to decrease the implementation cost. Therefore, the AES soft IP generator can also help users to reduce the time-to-market efficiently, and optimized the system in the SOC design.