• DocumentCode
    3066281
  • Title

    A system level integration methodology for MPEG-2 audio decoder with embedded RISC core

  • Author

    Tsai, Tsung-Han ; Chen, Liang-Gee ; Wu, Ren-Jr

  • Author_Institution
    Dept. of Electr. Eng., Hwa Hsia Coll. of Technol. & Commerce, Taiwan
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    46
  • Lastpage
    49
  • Abstract
    MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4×6.4 mm2, and the tested chip can run at maximum 43.5 MHz clock rate
  • Keywords
    application specific integrated circuits; audio coding; decoding; embedded systems; reduced instruction set computing; 43.5 MHz; MPEG-2 audio decoder algorithm; embedded RISC core; semi-ASIC architecture; standard cell; system level integration; Application specific integrated circuits; Computer architecture; Costs; Decision making; Decoding; Educational institutions; Filter bank; Frequency synchronization; Hardware; Reduced instruction set computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems, and Applications, 1999. International Symposium on
  • Conference_Location
    Taipei
  • ISSN
    1524-766X
  • Print_ISBN
    0-7803-5620-9
  • Type

    conf

  • DOI
    10.1109/VTSA.1999.785996
  • Filename
    785996
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3066281