Modeling the impact of back-end process variation on circuit performance

Author

Sylvester, Dennis ; Nakagawa, O. Sam ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1999

fDate

1999

Firstpage

58

Lastpage

61

Abstract

We present a stochastic approach to account for on-chip interconnect process variation. A Monte Carlo approach is taken using actual process distributions to generate realistic 3-D performance corners. Accurate analytical models are used to provide a >3 order of magnitude speedup over simulation techniques. Resulting delay and noise performance spreads are 33 to 63% tighter than those found using a conventional technique. We apply this method to a clock distribution network to more precisely determine clock skew

Keywords

CMOS digital integrated circuits; Monte Carlo methods; SPICE; ULSI; crosstalk; delays; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; 3-D performance corners; Monte Carlo approach; ULSI; analytical models; back-end process variation; circuit performance; clock distribution network; clock skew; crosstalk; deep submicron CMOS; delay performance spread; noise performance spread; on-chip interconnect modeling; process distributions; stochastic approach; Analytical models; Circuit optimization; Clocks; Crosstalk; Delay; Integrated circuit interconnections; Monte Carlo methods; Stochastic resonance; Ultra large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.785999

Filename

785999