An efficient method for the decomposition and resynthesis of speed-independent circuits

Author

Chen, Ren-Der ; Jou, Jer-Min

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1999

fDate

1999

Firstpage

62

Lastpage

65

Abstract

This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders of magnitude, and the implementation area is also reduced

Keywords

Petri nets; asynchronous circuits; hazards and race conditions; logic design; area efficient method; asynchronous benchmark circuits; decomposition; hazard-free decomposition; high-fanin gates; implementation area reduction; resynthesis; signal transition graph specification; signal-adding methods; speed-independent circuits; time efficient method; Asynchronous circuits; Circuit synthesis; Delay; Fires; Hazards; Libraries; Logic functions; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786000

Filename

786000