Title :
An efficient synthesizer for generation of fast parallel multipliers
Author :
Hsiao, Shen-Fu ; Jiang, Ming-Rong
Author_Institution :
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
An automatic generator is developed which can synthesize fixed-point multipliers of any bit accuracy with speed performance comparable to other recent full-custom designs. This synthesizer performs global optimization on the interconnection of compression elements to minimize the delay in the partial product summation tree
Keywords :
circuit layout CAD; circuit optimisation; delays; fixed point arithmetic; integrated circuit layout; logic CAD; multiplying circuits; trees (mathematics); VLSI arithmetic; automatic generator; compression element interconnection; data path synthesizer; delay minimization; fast parallel multipliers; fixed-point multipliers; gate-level Verilog output; global optimization; partial product summation tree; physical layout; speed performance; Adders; Arithmetic; Compressors; Counting circuits; Delay; Hardware design languages; Indexing; Integrated circuit interconnections; Synthesizers; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786001
