DocumentCode
3066382
Title
A scaling procedure for Domino CMOS logic
Author
Wurtz, Larry
Author_Institution
Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
fYear
1992
fDate
12-15 Apr 1992
Firstpage
580
Abstract
The area required by domino CMOS gates to support a specific response-time performance and capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI Domino CMOS gates. The scaling procedure has resulted in scaled NFET widths very close to those obtained by Monte Carlo techniques and SPICE
Keywords
CMOS integrated circuits; Monte Carlo methods; SPICE; integrated logic circuits; logic gates; Domino CMOS AND gate; Domino CMOS AOI gate; Domino CMOS OAI gate; Domino CMOS logic; Monte Carlo techniques; NFET chain; SPICE; capacitive load; response-time performance; scaling procedure; CMOS logic circuits; CMOS process; CMOS technology; Delay; Fabrication; Inverters; Parasitic capacitance; SPICE; Semiconductor device modeling; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Southeastcon '92, Proceedings., IEEE
Conference_Location
Birmingham, AL
Print_ISBN
0-7803-0494-2
Type
conf
DOI
10.1109/SECON.1992.202258
Filename
202258
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