Title :
A scaling procedure for Domino CMOS logic
Author_Institution :
Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
Abstract :
The area required by domino CMOS gates to support a specific response-time performance and capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI Domino CMOS gates. The scaling procedure has resulted in scaled NFET widths very close to those obtained by Monte Carlo techniques and SPICE
Keywords :
CMOS integrated circuits; Monte Carlo methods; SPICE; integrated logic circuits; logic gates; Domino CMOS AND gate; Domino CMOS AOI gate; Domino CMOS OAI gate; Domino CMOS logic; Monte Carlo techniques; NFET chain; SPICE; capacitive load; response-time performance; scaling procedure; CMOS logic circuits; CMOS process; CMOS technology; Delay; Fabrication; Inverters; Parasitic capacitance; SPICE; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Southeastcon '92, Proceedings., IEEE
Conference_Location :
Birmingham, AL
Print_ISBN :
0-7803-0494-2
DOI :
10.1109/SECON.1992.202258
